Verilog Coding for Logic Synthesis

Verilog Coding for Logic Synthesis

Weng Fook Lee
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Appropriate for both students and practicing engineers, this book outlines the syntax of the Verilog hardware description language for designing application-specific integrated circuit (ASIC) chips, and describes the common practices and coding style used when coding for synthesis. The second half of the book applies Verilog coding to the design of a programmable timer and a programmable logic block for peripheral interface. Topics include comments, Verilog data types, primitives, clock generation, Verilog operators, and the state machine.
Kategori:
Tahun:
2003
Penerbit:
Wiley-Interscience
Bahasa:
english
Halaman:
334
ISBN 10:
0471429767
ISBN 13:
9780471429760
Fail:
PDF, 1.28 MB
IPFS:
CID , CID Blake2b
english, 2003
Memuat turun (pdf, 1.28 MB)
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